Intel releases its 2023-2025 Xeon processor roadmap: dividing the production line by P-core and E-core and pushing 4 products in 2 years

Update time : 2023-03-30 15:57:51

Since 2017, AMD has been steadily gaining market share in server processors with its EPYC processors. At the same time, various processors based on the Arm architecture have started to rise, and while Intel maintains its leading position, its market share is declining. For many investors, Intel's data centre business is where its biggest concern lies.

Intel just announced its 2023-2025 Xeon processor roadmap today, focusing on its data center and artificial intelligence business units, while providing extensive updates on Intel's latest market forecasts, hardware plans, and ways to license developers through software.
According to Intel, the future of the Xeon family of processors will be divided into two series of product lines, P-Core and E-Core, the former being the previous traditional Xeon series, and the latter being a new addition to the energy-efficient architecture that will provide better power efficiency, with the initial generation being the previously announced Sierra Forest. Intel has chosen to do this mainly to meet different types of customer needs.
The fourth generation of Xeon Scalable processors, the Sapphire Rapids, which succeeds the Emerald Rapids, has been prototyped and is undergoing volume validation and is expected to be delivered on schedule in the fourth quarter of this year. It still uses the Eagle Stream platform, which remains compatible with Sapphire Rapids, in the same LGA-4677 socket, allowing customers to upgrade seamlessly.
Emerald Rapids remains on the 10nm Enhanced SuperFin process, the Intel 7 process, and switches to the Raptor Cove architecture cores, an optimized version of the Golden Cove architecture, which is expected to offer a 5% to 10% IPC increase, up to 64 cores and 128 threads, and an increased base frequency of 2.6 GHz, with 320MB of L3 cache and 128MB of L2 cache, support for up to 4TB of DDR5-5600 memory, and an increased TDP of 375W.
The real qualitative change is Granite Rapids, which will be released in 2024, following Sierra Forest, based on the Intel 3 process, using Redwood Cove architecture cores, and will increase the number of cores and threads, expected to reach 120 cores and 240 threads, with 240MB of L3 cache. Granite Rapids will have a base frequency of 2.5 GHz and offer 128 lanes of PCIe 6.0 as well as 12 lanes of DDR5 memory. Intel has revealed that Granite Rapids will contain multiple small chips in a single SoC, packaged via EMIB.
Intel will enable Mountain Stream and Birch Stream platforms, the latter for high-end Xeon chips, in favor of the LGA-7529 socket. Notably, Granite Rapids has breakthroughs in memory and I/O. Memory is even supported up to DDR5-8800 MCR RIDMM, and the maximum bandwidth is a staggering 1.5TB/s, an 83% improvement.
Intel plans to launch Sierra Forest in the first half of 2024, an all-E-Core offering with 144 cores, manufactured using the Intel 3 process and using the LGA-7529 socket. Sierra Forest has the advantage of a higher core count compared to rival AMD codenamed Bergamo with up to 128 cores of Zen4c architecture. Sierra Forest is understood to be specifically optimized for end-cloud workloads and has already come out with samples and successfully lit up. With a shared platform, IP, and technology with Granite Rapids, development and design time are minimized.
Intel also gave a brief overview of the second generation of all-E-Core processors, called Clearwater Forest, scheduled for 2025 and built on the Intel 18A process, which will feature more cores. The former is an implementation of Gate All Around transistors, which will be Intel's first new transistor architecture since the introduction of FinFET in 2011, accelerating transistor switching speeds while achieving the same drive current as multi-fin structures but in a smaller footprint; the latter is Intel's unique and industry-first backside power transfer network that optimizes signal transfer by eliminating the need for front-side power supply wiring on wafers.

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