Name: W9751G6KB-25 Supplier,stock W9751G6KB-25,SIC electronics ship on the same day
Brand: Electronic components distributor,SIC electronics stock delivery on the same day
SKU: W9751G6KB-25
Availability: InStock

We use cookies to improve your online experience. By continuing browsing this website, we assume you agree our use of cookies.

RFQ List (0item)

Submit

In Stock : 10807

Please send RFQ, we will respond immediately.

GENERAL DESCRIPTION
The W9751G6KB is a 512M bits DDR2 SDRAM, organized as 8,388,608 words  4 banks  16 bits.This device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for generalapplications. W9751G6KB is sorted into the following speed grades: -18, 18I, -25, 25L, 25I and -3. The-18/18I grade parts are compliant to the DDR2-1066 (7-7-7) specification (the 18I industrial gradewhich is guaranteed to support -40°C ≤ TCASE ≤ 95°C). The -25/25L/25I grade parts are compliant tothe DDR2-800 (5-5-5) or DDR2-800 (6-6-6) specification (the 25I industrial grade which is guaranteedto support -40°C ≤ TCASE ≤ 95°C). The -3 grade parts is compliant to the DDR2-667 (5-5-5)specification.
All of the control and address inputs are synchronized with a pair of externally supplied differentialclocks. Inputs are latched at the cross point of differential clocks (CLK rising andCLKfalling). AllI/Os are synchronized with a single ended DQS or differential DQS- DQSpair in a sourcesynchronous fashion.

FEATURES
 Power Supply: VDD, VDDQ = 1.8 V ± 0.1V
 Double Data Rate architecture: two data transfers per clock cycle
 CAS Latency: 3, 4, 5, 6 and 7 Burst Length: 4 and 8
 Bi-directional, differential data strobes (DQS andDQS) are transmitted / received with data
 Edge-aligned with Read data and center-aligned with Write data
 DLL aligns DQ and DQS transitions with clock
 Differential clock inputs (CLK andCLK)
 Data masks (DM) for write data
 Commands entered on each positive CLK edge, data and data mask are referenced to both edgesof DQS
 PostedCASprogrammable additive latency supported to make command and data bus efficiency
 Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
 Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signalquality
 Auto-precharge operation for read and write bursts
 Auto Refresh and Self Refresh modes
 Precharged Power Down and Active Power Down
 Write Data Mask
 Write Latency = Read Latency - 1 (WL = RL - 1)
 Interface: SSTL_18
 Packaged in WBGA 84 Ball (8X12.5 mm2), using Lead free materials with RoHS compliant

***************************************************************
FOR MORE DETAILS , PLEASE CONTACT US, THANK YOU.
Email: [email protected]

1. Purchase

You can send an inquiry by email,or add the item to the RFQ list and submit it to us.

Tell us the model and quantity you need,our sales staff will reply the price in time.

Email for receiving inquiries:[email protected]

2. Means of Payment

For your convenience,we accept multiple payment methods in USD,including PayPal,Credit Card,and wire transfer.

3. RFQ(Request for Quotations)

It is recommended to request for quotations to get the latest prices and inventories about the part.

Our sales will reply to your request by email within 24 hours.

IMPORTANT NOTICE

1. You'll receive an order information email in your inbox. (Please remember to check the spam folder if you didn't hear from us).

2. Since inventories and prices may fluctuate to some extent,the sales manager is going to reconfirm the order and let you know if there are any updates.

4. Shipping Cost

Shipping starts at $40,but some countries will exceed S40. For example (South Africa,Brazil,India,Pakistan,Israel,etc.)

The basic freight (for package ≤0.5kg or corresponding volume)depends on the time zone and country.

Shipping Method

Currently,our products are shipped through DHL,FedEx,SF,and UPS.

Delivery Time

Once the goods are shipped,estimated delivery time depends on the shipping methods you chose:

FedEx International,5-7 business days.