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Home > Industry News

AMD's largest chip release: integrated 13 small chips, 146 billion transistors, and improved AI performance by 8 times

Update time : 2023-01-14 11:49:02

On January 6, it was reported that AMD launched the next generation APU product Instanct MI300 for the data center at CES 2023, which is designed by chiplet, with 13 small chips and 146 billion transistors.

Specifically, the Instinct MI300 is composed of 13 small chips, many of which are based on 3D stacking, have 24 Zen4 CPU cores, integrate CDNA 3 graphics engines, and share a unified memory pool, including Infinity Cache cache and 8 HBM shared memory designs. In general, the chip has 146 billion transistors, surpassing Intel's Ponte Vecchio with 100 billion transistors and becoming the largest chip put into production by AMD.
From the exposed photos, we can see that there are eight HBM3 chips with a total of 128GB on both sides of the MI300, and a number of silicon chips with small structures are placed between these HBM3 chips to ensure the stability of the cooling solution when it is tightened on the top of the package.
The computing part of the MI300 consists of nine microchips based on TSMC's 5nm process. These microchips include CPU and GPU cores, but AMD does not provide detailed information about each microchip.
Since the Zen 4 core is usually deployed with eight cores, a 24 core CPU means that three small chips are CPU chips and the other six are GPU chips. The GPU chip uses AMD's CDNA 3 architecture, which is the third version of AMD's data center specific graphics architecture. AMD has not yet determined the number of CU, but official data shows that the AI performance per watt of CDNA 3 is five times that of the previous generation CDNA 2.
These nine small chips are stacked on four 6nm small chips through 3D packaging. These chips are not only passive intermediaries - these chips are active and can handle I/O and various other functions.
AMD representatives showed another MI300 sample, which polished the top mold to reveal the structure of the four active interlayer molds. You can clearly see the internal structures. These structures can not only communicate between I/O tiles, but also communicate with the memory controller of the HBM3 stack interface. However, no photos are allowed for this sample, so no photos can be provided.
The 3D stack design allows incredible data throughput between the CPU, GPU, and memory chips, while allowing the CPU and GPU to simultaneously process the same data in memory (zero copies), saving power, improving performance, and simplifying programming. It will be interesting to see if the device can be used without standard DRAM. As we saw in Intel's Xeon Max CPU, it also uses HBM on the package.
Representatives of AMD do not want to disclose more details, so it is unclear whether AMD uses the standard TSV method to connect the upper and lower chips together, or whether it uses a more advanced hybrid bonding method. AMD said that it would soon share more detailed information about packaging.
AMD claims that the AI performance and per watt performance provided by the MI300 are 8 times and 5 times that of the Instinct MI250 (using the sparse FP8 benchmark). AMD also said that it can reduce the training time of super large AI models such as ChatGPT and DALL-E from a few months to a few weeks, thereby saving millions of dollars in power.
The current generation of Instinct MI250 provides power for Frontier, the world's first megabyte supercomputer, and Instinct MI300 will provide power for the upcoming American new generation El Capitan supercomputer. Its FP64 peak computing performance reaches 20 billion times (2 ExaFLOPS).
AMD said that these MI300 chips for supercomputers will be expensive and relatively rare - these are not mass products, so they will not be widely deployed as EPYC Genoa data center CPUs. However, this technology will filter to multiple variants of different overall dimensions.
The chip will also compete with Nvidia's Grace Hopper Superchip, which integrates Hopper GPU and Grace CPU on the same substrate. The chips are expected to be available this year. The Grace CPU based on Neoverse is based on the Arm v9 instruction set and equipped with two chips integrated with NVLink-C2C interconnection technology of Nvidia's new brand. AMD's approach is designed to provide superior throughput and energy efficiency, because combining these devices into a single package can generally achieve higher throughput between cells than connecting two separate devices.
MI300 will also compete with Falcon Shores of Intel, which will have different numbers of computing modules, including x86 kernel, GPU kernel and memory, with dazzling possible configurations, but these will not come until 2024.
Here, we can see the bottom of the MI300 package, which contains contact pads for the LGA mounting system. AMD did not share more details, and the chip is currently in AMD's laboratory.
AMD is expected to deliver Instinct MI300 in the second half of 2023, when El Capitan Supercomputer will deploy MI300 for the first time, which is expected to become the fastest supercomputer in the world.
It is worth mentioning that Intel and Argonne National Laboratory are also deploying a supercomputer with an operation speed of up to 20 billion Aurora, which is based on Intel's Ponte Vecchio data center graphics card with more than 100 billion transistors.

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