Description
■ In System Control chapter:
– Clarified that an external LDO cannot be used.
– Clarified system clock requirements when the ADC module is in operation.
– Added important note to write the RCC register before the RCC2 register.
■ In Internal Memory chapter, clarified programming and use of the non-volatile registers.
■ In GPIO chapter, corrected "GPIO Pins With Non-Zero Reset Values" table and added note that ifthe same signal is assigned to two different GPIO port pins, the signal is assigned to the port withthe lowest letter.
■ In EPI chapter:
– Clarified table "Capabilities of Host Bus 8 and Host Bus 16 Modes".
– Corrected bit and register resets for FREQ (Frequency Range) in EPI SDRAM Configuration(EPISDRAMCFG) register.
– Corrected bit and register resets for MAXWAIT (Maximum Wait) in EPI Host-Bus 8 Configuration(EPIHB8CFG) and EPI Host-Bus 16 Configuration (EPIHB16CFG) registers. Also clarifiedbit descriptions in these registers.
– Corrected bit definitions for the EPSZ and ERSZ bits in the EPI Address Map (EPIADDRMAP)register.
– Corrected size of COUNT bit field in EPI Read FIFO Count (EPIRFIFOCNT) register.
■ In Timer chapter, clarified timer modes and interrupts.
■ In ADC chapter, added "ADC Input Equivalency Diagram".
■ In UART chapter, clarified interrupt behavior.
■ In SSI chapter, corrected SSIClk in the figure "Synchronous Serial Frame Format (Single Transfer)"and clarified behavior of transmit bits in interrupt registers.
■ In I2C chapter, corrected bit and register reset values for IDLE bit in I2C Master Control/Status(I2CMCS) register.
■ In USB chapter:
– Clarified that when the USB module is in operation, MOSC must be provided with a clock source,and the system clock must be at least 30 MHz.
– Removed MULTTRAN bit from USB Transmit Hub Address Endpoint n (USBTXHUBADDRn)and USB Receive Hub Address Endpoint n (USBRXHUBADDRn) registers.
– Corrected description for the USB Device RESUME Interrupt Mask (USBDRIM) register.
■ In Analog Comparators chapter, clarified internal reference programming.
■ In PWM chapter, clarified PWM Interrupt Enable (PWMINTEN) register description.
■ In Signal Tables chapter, clarified VDDC and LDO pin descriptions.
■ In Electrical Characteristics chapter:
– In Maximum Ratings table, deleted parameter "Input voltage for a GPIO configured as an analoginput".
– In Recommended DC Operating Conditions table, corrected values for IOH parameter.
– In JTAG Characteristics, table, corrected values for parameters "TCK clock Low time" and "TCKclock High time".
– In LDO Regulator Characteristics table, added clarifying footnote to CLDO parameter.
– In System Clock Characteristics with ADC Operation table, added clarifying footnote to Fsysadcparameter.
– Added "System Clock Characteristics with USB Operation" table.
– In Sleep Modes AC Characteristics table, split parameter "Time to wake from interrupt" intosleep mode and deep-sleep mode parameters.
– In SSI Characteristics table, corrected value for parameter "SSIClk cycle time".
– In Analog Comparator Characteristics table, added parameter "Input voltage range" and correctedvalues for parameter "Input common mode voltage range".
– In Analog Comparator Voltage Reference Characteristics table, corrected values for absoluteaccuracy parameters.
– Deleted table "USB Controller DC Characteristics".
– In Nominal Power Consumption table, added parameter for sleep mode.
– In Maximum Current Consumption section, changed reference value for MOSC and temperaturein tables that follow.
– Deleted table "External VDDC Source Current Specifications".
■ Additional minor data sheet clarifications and corrections.
■ Corrected "Reset Sources" table.
■ Added missing PICAL (PIOSC Calibrate) bit to DC4 register.
■ Added Important Note that RCC register must be written before RCC2 register.
■ In Hibernation Module chapter, deleted section "Special Considerations When Using a 4.194304-MHzCrystal" as the content was added to the errata document.
■ Added a note that all GPIO signals are 5-V tolerant when configured as inputs except for PB0 andPB1, which are limited to 3.6 V.
■ Note that the state of the HSE bit in the UARTCTL register has no effect on clock generation in ISO7816 smart card mode (when the SMART bit in the UARTCTL register is set).
■ Corrected LIN Mode bit names in UART Interrupt Clear (UARTICR) register.
■ Corrected pin number for RST in table "Connections for Unused Signals" (other pin tables werecorrect).
■ In the "Operating Characteristics" chapter:
– In the "Thermal Characteristics" table, the Thermal resistance value was changed.
– In the "ESD Absolute Maximum Ratings" table, the VESDCDM parameter was changed and theVESDMM parameter was deleted.
■ The "Electrical Characteristics" chapter was reorganized by module. In addition, some of theRecommended DC Operating Conditions, LDO Regulator, Clock, GPIO, EPI, ADC, and SSIcharacteristics were finalized.
■ Added missing ordering table.
■ Additional minor data sheet clarifications and corrections.
■ Clarified Main Oscillator verification circuit sequence.
■ Added note that there must be a delay of 3 system clocks after the module clock is enabled beforeany of that module's registers are accessed. Also added note to add delay between powering-onthe Ethernet PHY and accessing it.
■ Added "Example Schematic for Muxed Host-Bus 16 Mode" figure to External Peripheral Interface(EPI) chapter.
■ Corrected reset of Device Mode (DEVMOD) bitfield in USB General-Purpose Control and Status(USBGPCS) register.
■ Clarified initialization and configuration procedure in "Analog Comparators" chapter.
■ In Electrical Characteristics chapter:
– Added specification for maximum input voltage on a non-power pin when the microcontroller isunpowered (VNON parameter in Maximum Ratings table).
– Replaced Preliminary Current Consumption Specifications with Nominal Power Consumption,Maximum Current Specifications, and Typical Current Consumption vs. Frequency sections.
– Clarified Reset, and Power and Brown-out Characteristics and added a new specification forpowering down before powering back up.
– Added characteristics required when using an external regulator to provide power for VDDC.
■ Additional minor data sheet clarifications and corrections.
■ Information on Advanced Encryption Standard (AES) cryptography tables and Cyclic RedundancyCheck (CRC) error detection functionality was inadvertently omitted from some datasheets. Thishas been added.
■ In APINT register, changed bit name from SYSRESETREQ to SYSRESREQ.
■ Added DEBUG (Debug Priority) bit field to SYSPRI3 register.
■ Clarified Flash memory caution.
■ Restructured the General-Purpose Timer chapter to combine duplicated text.
■ Combined High and Low bit fields in GPTMTAILR, GPTMTAMATCHR, GPTMTAR, GPTMTAV,GPTMTBILR, GPTMTAMATCHR, GPTMTBR and GPTMTBV registers for compatibility with futurereleases.
■ Removed mention of false-start bit detection in the UART chapter. This feature is not supported.
■ Added SSI master clock restriction that SSIClk cannot be faster than 25 MHz.
■ Changed I2C master and slave register base addresses and offsets to be relative to I2C modulebase, so register base and offsets were changed for all I2C slave registers.
■ In Electrical Characteristics chapter:
– Added single-ended clock source input voltage values to "Recommended DC OperatingConditions" table.
– Deleted Oscillation mode value from "MOSC Oscillator Input Characteristics" table.
– Added TVDD2_3 supply voltage parameter to "Reset Characteristics" table.
– Added "Power-On Reset and Voltage Parameters" timing diagram.
– Added tALEADD parameter to "EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics" table.
– Added "Host-Bus 8/16 Mode Muxed Read Timing" and "Host-Bus 8/16 Mode Muxed WriteTiming" timing diagrams.
■ Reorganized ARM Cortex-M3 Processor Core, Memory Map and Interrupts chapters, creating twonew chapters, The Cortex-M3 Processor and Cortex-M3 Peripherals. Much additional content wasadded, including all the Cortex-M3 registers.
■ Changed register names to be consistent with StellarisWare®names: the Cortex-M3 InterruptControl and Status (ICSR) register to the Interrupt Control and State (INTCTRL) register, andthe Cortex-M3 Interrupt Set Enable (SETNA) register to the Interrupt 0-31 Set Enable (EN0)register.
■ In the System Control chapter:
– Corrected Reset Sources table (see Table 5-3 on page 200).
– Added section "Special Considerations for Reset."
■ In the Internal Memory chapter:
– Added clarification of instruction execution during Flash operations.
– Deleted ROM Version (RMVER) register as it is not used.
■ Modified Figure 8-1 on page 408 and Figure 8-2 on page 409 to clarify operation of the GPIO inputswhen used as an alternate function.
■ Corrected GPIOAMSEL bit field in GPIO Analog Mode Select (GPIOAMSEL) register to be eight-bitswide, bits[7:0].
■ In General-Purpose Timers chapter, clarified operation of the 32-bit RTC mode.
■ In CAN chapter, clarified CAN bit timing examples.
■ In Operating Characteristics chapter, corrected Thermal resistance (junction to ambient) value to32.
■ In Electrical Characteristics chapter:
– Added "Input voltage for a GPIO configured as an analog input" value to Table 26-1 on page 1311.
– Added ILKG parameter (GPIO input leakage current) to Table 26-17 on page 1320.
– Corrected reset timing in Table 26-5 on page 1315.
– Specified Max value for VREFA in Table 26-23 on page 1327.
– Corrected values for tCLKRF (SSIClk rise/fall time) in Table 26-25 on page 1327.
– Added I2C Characteristics table (see Table 26-26 on page 1329).
■ Added dimensions for Tray and Tape and Reel shipping mediums.
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