Introduction
The Spartan®-3E family of Field-Programmable GateArrays (FPGAs) is specifically designed to meet the needsof high volume, cost-sensitive consumer electronicapplications. The five-member family offers densitiesranging from 100,000 to 1.6 million system gates, as shownin Table 1.The Spartan-3E family builds on the success of the earlierSpartan-3 family by increasing the amount of logic per I/O,significantly reducing the cost per logic cell. New featuresimprove system performance and reduce the cost ofconfiguration. These Spartan-3E FPGA enhancements,combined with advanced 90 nm process technology, delivermore functionality and bandwidth per dollar than waspreviously possible, setting new standards in theprogrammable logic industry.Because of their exceptionally low cost, Spartan-3E FPGAsare ideally suited to a wide range of consumer electronicsapplications, including broadband access, homenetworking, display/projection, and digital televisionequipment.The Spartan-3E family is a superior alternative to maskprogrammed ASICs. FPGAs avoid the high initial cost, thelengthy development cycles, and the inherent inflexibility ofconventional ASICs. Also, FPGA programmability permitsdesign upgrades in the field with no hardware replacementnecessary, an impossibility with ASICs.
Features
• Very low cost, high-performance logic solution forhigh-volume, consumer-oriented applications
• Proven advanced 90-nanometer process technology
• Multi-voltage, multi-standard SelectIO™ interface pins
• Up to 376 I/O pins or 156 differential signal pairs
• LVCMOS, LVTTL, HSTL, and SSTL single-ended signalstandards
• 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
• 622+ Mb/s data transfer rate per I/O
• True LVDS, RSDS, mini-LVDS, differential HSTL/SSTLdifferential I/O
• Enhanced Double Data Rate (DDR) suppor
t• DDR SDRAM support up to 333 Mb/s
• Abundant, flexible logic resources
• Densities up to 33,192 logic cells, including optional shiftregister or distributed RAM support
• Efficient wide multiplexers, wide logic
• Fast look-ahead carry logic
• Enhanced 18 x 18 multipliers with optional pipeline
• IEEE 1149.1/1532 JTAG programming/debug port
• Hierarchical SelectRAM™ memory architecture
• Up to 648 Kbits of fast block RAM
• Up to 231 Kbits of efficient distributed RAM
• Up to eight Digital Clock Managers (DCMs)
• Clock skew elimination (delay locked loop)
• Frequency synthesis, multiplication, division
• High-resolution phase shifting
• Wide frequency range (5 MHz to over 300 MHz)
• Eight global clocks plus eight additional clocks per each halfof device, plus abundant low-skew routing
• Configuration interface to industry-standard PROMs
• Low-cost, space-saving SPI serial Flash PROM
• x8 or x8/x16 parallel NOR Flash PROM
• Low-cost Xilinx® Platform Flash with JTAG
• Complete Xilinx ISE® and WebPACK™ software
• MicroBlaze™ and PicoBlaze embedded processor cores
• Fully compliant 32-/64-bit 33 MHz PCI support (66 MHz insome devices)
• Low-cost QFP and BGA packaging options
• Common footprints support easy density migration
• Pb-free packaging options• XA Automotive version available
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